1. Technical Field
A clock enable buffer is disclosed which can reduce current consumption and malfunction due to noise, and which can be used in a stub-series terminated logic (hereinafter, referred to as ‘SSTL’) interface, while using a differential buffer.
2. Discussion of Related Art
JEDEC rules entry and exit at the time of a self-refresh mode of semiconductor memory devices such as DRAMs. In other words, according to the rules, the entry refers to what a clock enable signal (CKE) shifts from a High level to a Low level and the exit refers to what the clock enable signal (CKE) shifts from a Low level to a High level.
An important thing relating to such a self-refresh entry is to use a circuit that can consume only a minimum current, which may be used in DRAMs. An input buffer used at the time of the self-refresh entry includes a static buffer that consumes a small amount of current. The static buffer has a possibility that malfunction may take place due to its property sensitive to noise and rarely uses a SSTL interface. As a differential buffer consumes a
For the above reason, a clock enable buffer uses a static buffer as shown in FIG. 2 in a self-refresh mode, which consumes 1000 times less current than a differential buffer, while using a differential buffer as shown in FIG. 1 in a normal mode, which consumes a large amount of current. At the time of the self-refresh entry, a modified differential buffer as shown in FIG. 3 instead of the static buffer may be used, but it also consumes a great amount of current.
FIG. 1 is a detailed circuit diagram showing a differential buffer used in a normal mode in a related art.
Referring to FIG. 1, if a self-refresh signal (sref) is Low, the output of an inverter I1 becomes a High level and an NMOS transistor N3 is thus turned on. Therefore, if a clock enable signal (CKE) is High, i.e., the clock enable signal (CKE) is higher than a reference voltage (vref), an NMOS transistor N1 is turned on earlier than an NMOS transistor N2. Accordingly, the output (Vout1) becomes a Low level.
Meanwhile, if the clock enable signal (CKE) is lower than the reference voltage (vref), the NMOS transistor N2 is turned on earlier than the NMOS transistor N1. The output (Vout1) thus becomes a High level. As a result, PMOS transistors P1 and P2 functions as a load for supplying a static voltage.
FIG. 2 is a detailed circuit diagram of a static buffer that consumes 1000 times less current than the differential buffer as shown in FIG. 1.
If a self-refresh signal (sref) is High, an NMOS transistor N5 is turned on, while a PMOS transistor P4 is turned off. If a clock enable signal (CKE) is Low, a PMOS transistor P3 is turned on and an output (Vout2) thus becomes a High level.
Meanwhile, if the clock enable signal (CKE) is High, the PMOS transistor P3 is turned off and the output (Vout2) thus becomes a Low level.
A delay unit 10 is for allowing the static buffer to operate after a given delay time since the differential buffer is turned off upon entry of a self-refresh mode. That is, the delay unit 10 functions to prevent two buffers from operating at the same time.
In order to reduce malfunction due to noise and for a SSTL interface to be used, a differential buffer as shown in FIG. 3 may be used instead of the circuit as shown in FIG. 2, upon entry of the self-refresh mode.
The operation of such a differential buffer is same as that of the circuit shown in FIG. 1. A delay unit 20 is for allowing the static buffer to operate after a given delay time since the differential buffer is turned off upon entry of the self-refresh mode. That is, the delay unit 20 functions to prevent two buffers from operating at the same time.
A region (A) in FIG. 4 is a period where the clock enable signal (CKE) is High and the self-refresh mode is Low. During this period, the differential buffer is operated. A region (B) is a period where the clock enable signal (CKE) is Low and the self-refresh mode is High. During this period, the static buffer is operated.
As described above, if the static buffer is used as the clock enable buffer upon entry of the self-refresh mode, there are problems that a circuit is greatly affected by noise and does not use the SSTL interface. If the differential buffer is used, there is a disadvantage that a great amount of power is consumed.